Test MP+dmb.sy+addr-[fr-rf]-data-rfi-addr

AArch64 MP+dmb.sy+addr-[fr-rf]-data-rfi-addr
"DMB.SYdWW Rfe DpAddrdR FrLeave RfBack DpDatadW Rfi DpAddrdR Fre"
Cycle=Rfi DpAddrdR Fre DMB.SYdWW Rfe DpAddrdR FrLeave RfBack DpDatadW
Relax=
Safe=Rfi Rfe Fre DMB.SYdWW DpAddrdR DpDatadW [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpAddrdR FrLeave RfBack DpDatadW Rfi DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X7=a; 1:X11=x;
2:X1=z;
}
 P0          | P1                    | P2          ;
 MOV W0,#1   | LDR W0,[X1]           | MOV W0,#1   ;
 STR W0,[X1] | EOR W2,W0,W0          | STR W0,[X1] ;
 DMB SY      | LDR W3,[X4,W2,SXTW]   |             ;
 MOV W2,#1   | LDR W5,[X4]           |             ;
 STR W2,[X3] | EOR W6,W5,W5          |             ;
             | ADD W6,W6,#1          |             ;
             | STR W6,[X7]           |             ;
             | LDR W8,[X7]           |             ;
             | EOR W9,W8,W8          |             ;
             | LDR W10,[X11,W9,SXTW] |             ;
Observed
    z=1; y=1; x=1; a=1; 1:X8=1; 1:X5=0; 1:X3=1; 1:X10=1; 1:X0=1;
and z=1; y=1; x=1; a=1; 1:X8=1; 1:X5=0; 1:X3=1; 1:X10=0; 1:X0=1;
and z=1; y=1; x=1; a=1; 1:X8=1; 1:X5=0; 1:X3=1; 1:X10=1; 1:X0=0;
and z=1; y=1; x=1; a=1; 1:X8=1; 1:X5=0; 1:X3=1; 1:X10=0; 1:X0=0;